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AR# 55077 Ethernet IP - Design hierarchy in Vivado tools

Ethernet IP cores in Vivado have been updated to be delivered as a core block containing both encrypted HDL and GT instances. 

The previous 'core block' level is now the top level of the core. This includes transceiver instances and physical interface I/O logic. The transceiver instances, IOBs and supporting logic are still delivered as plain HDL. There is also a core level hierarchical XDC file.  For more information about the block level ports, please consult the core Product Guide.
AR# 55077
Date Created
Last Updated 04/01/2013
Status Active
Type General Article
IP
  • 10 Gigabit Ethernet Media Access Controller
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
  • Ethernet 1000BASE-X PCS/PMA or SGMII
  • More
  • QSGMII
  • RXAUI
  • Ten Gigabit Ethernet PCS/PMA
  • Tri-Mode Ethernet MAC
  • XAUI
  • Less
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