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AR# 55090

Vivado Power Solution Center - Design Advisory


The Power Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.
To update your Xilinx Alert Notification Preferences, please go to:

Note: The article is part of the Power Solution Center. The Power solution center for Xilinx Devices is available to address questions related to Power.

Whether you are starting a new design with any Xilinx devices or trouble shooting any power related problems, use this Power solution center to guide you and simplify your work. 


The following are Design Advisory articles related to power:
(Xilinx Answer 61748)  - Design Advisory Vivado Power/XPE - GTH - LPM/DFE mode under-reporting for MGTAVcc current in XPE
(Xilinx Answer 47443) - Design Advisory for 7 Series FPGA GTH transceiver Power
(Xilinx Answer 43889) - 13.2 7-series XPE: Issue to Estimate Power in Bank 0 with HP-only device 
(Xilinx Answer 37667) - Virtex-6 FPGA -1L Industrial Grade Vccint Specification Change 
(Xilinx Answer 37006) - Techniques to achieve required FPGA power-up sequencing

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
55087 Vivado Power Solution Center N/A N/A
AR# 55090
Date Created 03/24/2013
Last Updated 02/16/2016
Status Active
Type Design Advisory
  • Vivado Design Suite