Urgency : Standard
The following warning/error occured when running trce on a
WARNING:bastw:169 - Pulse-width error at comp (mapped physical logic
cell) "ref_clk_77mhz" for signal "fpga_refclk". The pulse width for this
signal is less than the minimum pulse-width specification for the pin on
comp "ref_clk_77mhz" to which the signal is connected. The pulse
width for signal "fpga_refclk" was calculated from the following
constraint in the PCF file:
NET "fpga_refclk" PERIOD = 6.430 nS HIGH 3.220 nS ;
Datasheet v1.1 on the web p.25 states that the min. clock pulse
width for -5 device (Tch and Tcl) is 2.3 ns.
The v1.1 datasheet on the web is outdated.
With the current speed file, Tch and Tcl for -5 is 3.312ns.
To get this information from the speed file, you can type the
speedprint xcv300 -s 6
Look for Tch and Tcl value.