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AR# 55123

2013 Vivado - IP Flows Known Issues


This answer record contains known issues for Vivado Design Suite 2013.x related to IP core flows, including IP customization, IP generation, IP Packager, IP Catalog and integration of IP cores in the Vivado design environment.


Outstanding Known IP Flow Issues in Vivado 2013.4

(Xilinx Answer 57046) - AXI ports from Vivado CPRI do not match IP Integrator AXI external ports
(Xilinx Answer 57882) - Create, Import Peripheral Wizard generated IP is missing the Support Narrow Burst parameter on the AXI4 Master Interface
(Xilinx Answer 58445) - "ERROR: [Vivado 12-563] The file type 'IP-XACT' is not user settable"
(Xilinx Answer 58939) - After modifying the IP configuration in IP Packager, the "Refresh" option is missing in the "IP GUI Customization Layout"

Known Issues Resolved in Vivado 2013.4

(Xilinx Answer 58525) - When I add an existing Block Diagram (BD), Vivado IDE appears to hang

Known Issues Resolved in Vivado 2013.3

(Xilinx Answer 52729) - Attempting to cancel an update of the IP catalog is unsuccessful
(Xilinx Answer 55128) - Launching an IP customization on SuSE 11, for a licensed IP results in =Abnormal program termination
(Xilinx Answer 56392) - Report_ip_status states "Newer version requires a different project part" for IP cores without an upgrade option in Vivado
(Xilinx Answer 56492) - Behavioral simulation fails (<core_name> not found) for designs with IP cores with a Design Check Point (DCP) generated in Vivado IDE
(Xilinx Answer 56519) - Interrupt sensitivity is not being populated correctly in the IP Integrator Interrupt Controller customize GUI
(Xilinx Answer 56538) - UART setting in XPS for a PS7 system are not preserved if "Preset Import" done in IPI
(Xilinx Answer 56539) - Bus interface property ID_WIDTH mis-match when mig_7series IP is connected to an AXI Interconnect
(Xilinx Answer 56584) - Changing AXI protocol in Interface properties is not getting reflected in HDL wrapper
(Xilinx Answer 56630) - License check fails for IP with old style license check (e.g., IP cores imported from ISE designs and certain 3rd party IP cores)
(Xilinx Answer 56634) - The get_files command is not returning all the files associated with an IP for source control
(Xilinx Answer 56696) - Vivado 2013.2 does not find the IP Design Linking (Simulation Only) licenses available with install
(Xilinx Answer 56819) - In Vivado IP Integrator (IPI) I cannot edit any options in Zynq7 Processing System v5.2 block
(Xilinx Answer 57168) - Assigning Zynq AXI_PCIe BAR1 address results in "ERROR: [BD 41-1202] <0x76000000[ 64K ]> is not within the addressable range..."
(Xilinx Answer 57333) - IP Integrator design "write_bd_tcl" generated "set_property" list for processing_system does not set all properties when sourced in new project
(Xilinx Answer 57753) - Help About screen doesn't show IP Build information

Known Issues Resolved in Vivado 2013.2

(Xilinx Answer 55293) - IP core port names have been converted to use all lower case characters in Vivado 2013.1
(Xilinx Answer 55436) - Warning message ([Designutils 20-729]) issues when generating an IP core which contains a sub-core
(Xilinx Answer 55726) - Upgrading certain Vivado IP cores results in "ERROR: [IP_Flow 19-503] Validation failed for parameter..."
(Xilinx Answer 55272) - An Internal Exception occurs when I open IP Catalog from the Getting Started section of the Vivado WebPACK edition
(Xilinx Answer 56102) - Coefficient files (.coe) for IP cores are stored with absolute path in XCI files.
AR# 55123
Date Created 03/25/2013
Last Updated 01/08/2014
Status Active
Type Known Issues
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2