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AR# 55134 MIG 7 Series - All interfaces have pll_locked and not mmcm_locked tied to their reset structure

Description

Version Found: v1.5
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)
All MIG 7 Series interfaces use a PLL and its LOCKED signals are tied into the reset structure. An additional MMCM was added starting with the MIG 7 series v1.5 (See (Xilinx Answer 47043)), but the LOCKED signal was not tied into the reset structure.

Solution

This is not expected to cause failures within the MIG designs but can be corrected by making the following changes within infrastructure.v:
change:

       assign rst_tmp_phaser_ref = sys_rst_act_hi | ~pll_locked_i | ~iodelay_ctrl_rdy;
to:

       assign rst_tmp_phaser_ref = sys_rst_act_hi | ~mmcm_locked | ~iodelay_ctrl_rdy;

Revision History
04/03/2013 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All Versions N/A N/A
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer versions N/A N/A

Actions

AR# 55134
Date Created
Last Updated 03/27/2013
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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