^
Advanced Search

AR# 55135 Vivado Synthesis - Unsupported SystemVerilog Constructs

Description

This answer record describes the SystemVerilog constructs and features that are not supported by Vivado Synthesis.

Solution

Vivado Synthesis does not support the following SystemVerilog supported constructs and features:

  • Alias
  • Arrays of Interfaces
  • Dynamic Arrays
  • Assert Statements
  • Class
  • Virtual Ports
  • Virtual Functions
  • Unpacked Unions
  • Tagged Unions in Loops

 

Actions

AR# 55135
Date Created 04/03/2013
Last Updated 04/03/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite
Feed Back