The timing failures only occur when using ISE and do not affect Vivado. To work around the timing violations the following code must be modified:
mig_7series_v1_9_rld_phy_write_init_sm.v
Replace:
(* max_fanout = "50" *)
reg [RST_SYNC_NUM-1:0] rst_clk_sync_r = -1;
with:
reg [RST_SYNC_NUM-2:0] rst_clk_sync_r = -1;
(* max_fanout = "50" *)
reg rst_clk_sync_r1 ;
Replace:
always @(posedge clk)
if (rst_wr_clk || !cnt_pwron_reset_done_r)
rst_clk_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_clk_sync_r <= #TCQ rst_clk_sync_r << 1;
assign rst_clk = rst_clk_sync_r[RST_SYNC_NUM-1];
with:
always @(posedge clk) begin
if (rst_wr_clk || !cnt_pwron_reset_done_r) begin
rst_clk_sync_r <= #TCQ {RST_SYNC_NUM-1{1'b1}};
rst_clk_sync_r1 <= #TCQ 1'b1;
end else begin
rst_clk_sync_r <= #TCQ rst_clk_sync_r << 1;
rst_clk_sync_r1 <= #TCQ rst_clk_sync_r [RST_SYNC_NUM-2];
end
end
assign rst_clk = rst_clk_sync_r1;
Revision History
04/03/2013 - Initial Release