We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55163

7 Series FPGAs Transceiver Wizard v2.5 - Known Issues and Release Notes


This answer record contains the Known Issues and Release Notes for the 7 series FPGAs Transceiver Wizard v2.5, released with the ISE 14.5 and Vivado 2013.1 design tools.


  * Version 2.5 
  * Native Vivado release
  * Support for Production Silicon for GTH and GTP.
  * New Protocol Templates added for GTH - SRIO multi lane, JESD204
  * New Protocol Templates added for GTP - JESD204

  • For GTH and GTP, the Wizard generates settings compatible for Production Silicon. Hardware validation of these settings is work in progress.
  • The Wizard generates Verilog wrappers for GTZ. VHDL is not supported.
  • Simulators supported for GTZ designs IUS and VCS.
  • For GTZ designs, the Wizard supports line rates and reference clocks shown in the GUI. No other values are tested or validated in hardware.
  • It is recommended that the Beachfront module generated for GTZ designs should NOT be modified by the user. Any edits made by the user might lead to unexpected results.
  • Please note that Vivado flow should be used for implementation of all SSIT devices.
  • Please note that the protocol templates provided by the Wizard are not characterized on hardware.
  • To simulate GTH and GTP Wrappers, the SIM_RESET_SPEEDUP parameter on the GT primitive should be set to false.
  • GTX Transceiver Wrappers generated for PCIE Gen2 protocol in VHDL have a known issue in functional simulation which is currently under investigation.
  • Post implementation functional and timing simulations are not supported for Transceiver wrappers generated for PCIE Gen1/Gen2 protocols.


Additional Resources:

For information on GTX Initial ES settings, see (Xilinx Answer 43244).

For information on GTH Initial ES settings, see (Xilinx Answer 47128).

For information on GTX General ES settings, see (Xilinx Answer 45360).

For information on GTH General ES settings, see (Xilinx Answer 51625).

For information on GTH Production Silicon settings, see (Xilinx Answer 53779).

For information on GTP Initial ES/General ES settings, see (Xilinx Answer 51369).

For information on GTP Production Silicon settings, see (Xilinx Answer 53561).

AR# 55163
Date 10/29/2013
Status Active
Type Release Notes
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
  • 7 Series FPGAs Transceivers Wizard
Page Bookmarked