Version Found: MIG 7 Series v1.9
Version Resolved: See (Xilinx Answer 54025)
The MIG 7 Series DDR3 design when implemented in Vivado design tools may show an abnormally high device utilization (and higher than an ISE implementation) and fail timing with errors similar to the following:
OUT_FIFO_X0Y9 OUT_FIFO (Prop_out_fifo_WRCLK_FULL)
0.391 3.548 r u_mig_7series_v1_9_a_0/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo/FULL
net (fo=1817, routed) 5.267 8.815 u_mig_7series_v1_9_a_0/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/I1
The high utilization and potential timing violations are due to max_fanout constraints within the generated MIG rtl. The max_fanout constraints are required for ISE implementation, but have been seen to cause both timing violations and an increase in flip-flop utilization with Vivado Synthesis.
When implementing a MIG 7 series design in the Vivado tool, the max_fanout constraints within the rtl can be removed. There are a number of max_fanout constraints within a number of MIG generated rtl modules.
This answer record includes a Tcl script that finds all max_fanout constraints within the rtl design and creates xdc constraints to override the rtl max_fanouts. This eliminates the need to manually update the rtl.
Download the Tcl script located at the bottom this answer record and follow the steps below to execute the script and properly update the design:
After completing these steps, a max_fanout.xdc file will be created. These constraints must now be added to the constraint set and the design re-synthesized by executing the following:
It is possible after completing these steps that critical warnings are issued on nets that were eliminated in the second pass through synthesis. If these warnings occur, they can be safely ignored as they are issued due to max_fanout assignments to non-existent nets. Otherwise, the nets with the critical warnings can be eliminated from the xdc file.
Note: The tcl script looks for MIG replicated cells based on the MIGcellFilter argument. If the default of mig is not part of the MIG path, run the following command to execute the script (instead of step 2.4):
mig_gen_max_fanout_xdc 30 XlnxMemoryController max_fanout.xdc
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