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AR# 55183

LogiCORE IP AXI Video Direct Memory Access v6.0 - Post-synthesis netlist simulation errors targeting defense grade or low power devices

Description

During post-synthesis or post-implementation netlist simulation of AXI VDMA v6.0 in Vivado 2013.1, the following behavior can occur and will result in error messages:

  • No forward progress is occurring on all channels.
    Transfers are not happening on theAXI4 Memory Mapped side of the VDMA.
     
  • Unexpected interrupt out.
    This occurs due to incorrect burst generation which crosses the 4KB boundary (prohibited by AXI4 spec).

Solution

This is a known issue that occurs in Vivado 2013.1 when using the AXI VDMA v6.0 targeting defense grade (q) devices or low power (l) devices. 

This issue is due to be fixed in the 2013.2 release.

To work around the problem, pass the root device family to the AXI VDMA rather than the sub-family. 

For specific details, see the following table:

Sub-Families Root Family
artix7l, qartix7, qartix7l artix7
kintex7l, qkintex7, qkintex7l kintex7
virtex7l, qvirtex7, qvirtex7l virtex7
azynq, qzynq zynq

 

Linked Answer Records

Master Answer Records

AR# 55183
Date Created 03/27/2013
Last Updated 08/27/2014
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Zynq-7000
Tools
  • Vivado Design Suite - 2013.1
IP
  • AXI Video Direct Memory Access
  • AXI Video DMA