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AR# 55199

How to set System Jitter in ISE (UCF)?

Description

How do I set System Jitter in ISE (UCF)?
 

Solution

ISE (UCF)
 
The System Jitter (SYSTEM_JITTER) constraint specifies the system jitter of the design.
System Jitter depends on various design conditions, such as the number of flip-flops changing at one time and the number of I/Os changing.
 
System Jitter applies to all clocks within a design.
System Jitter can be combined with the Input Jitter keyword on the Period constraint to generate the Clock Uncertainty value shown in the Timing Report.
 
 
SYSTEM_JITTER = <value> <units>;
 
 
Additional Information
 
 
AR# 55199
Date Created 03/27/2013
Last Updated 02/17/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite