UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55218

LogiCORE IP AXI Video Direct Memory Access - Horizontal shear/shift in output video

Description

I am using the AXI VDMA as a standard triple frame buffer, but I am seeing horizontal shear in the output video.

What could be the problem?

Solution

This might be caused by an improper setting of the Frame Delay parameter on the Genlock Slave (typically the MM2S side is Genlock Slave).

Please refer to the 'Triple Frame Buffer Example' in the product guide. As noted, the frame delay for the Genlock Slave should be set to 1. Note that it is set to 0 by default so you must manually make this change to the register.

Linked Answer Records

Master Answer Records

AR# 55218
Date Created 03/28/2013
Last Updated 09/12/2013
Status Active
Type General Article
IP
  • Video DMA
  • AXI Video Direct Memory Access
  • AXI Video DMA
  • AXI Video DMA