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AR# 55220

KC705 Connectivity TRD - DCLK frequency discrepancy with 10G Ethernet PCS/PMA PG


According to the 10-Gigabit Ethernet PCS/PMA core Product Guide (PG068 v2.6, page 23), dclk must run at exactly half the rate of clk156:


However, the example design for the KC705 Connectivity Kit TRD uses a 50MHz clock:






This is not an issue for the TRD PCS/PMA core because for BASE-R implementation this clock is only used for reading the PRBS errors. 

The TRD does not use these PRBS test patterns, so this discrepancy can be ignored. 

The dclk defined in the k7_connectivity_trd.v top level is used to feed 50 MHz clocks for several other modules such as the 10G MAC and GT Wizard cores, so do not modify this clock frequency.

Frequency DLKC=0.5*Frequency clk156 is a recommendation as that is how the IP team have accounted for domain crossing signals.

The correct clocking relationship has been implemented in 2013.1 release of the Kintex-7 Connectivity TRD.
AR# 55220
Date Created 03/28/2013
Last Updated 10/14/2014
Status Active
Type General Article
  • Kintex-7
  • 10 Gigabit Ethernet PCS-PMA with FEC/Auto-Negotiation for backplanes (10GBASE-KR)
Boards & Kits
  • Kintex-7 FPGA Connectivity Kit