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AR# 55248

Vivado Timing and IP Constraints - Why do I get the following CRITICAL WARNING: [Vivado 12-259] No clocks specified,​ please specify clocks, for my IP, or why do I get CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay?


Why do I get the following CRITICAL WARNINGs for the IP in my design?

The following is an example of the errors for a design that fails to find the clock constraint needed by a piece of IP.
CRITICAL WARNING: [Vivado 12-259] No clocks specified, please specify clocks using -clock, -fall_clock, -rise_clock options [C:/Design/v_tc.xdc:1]
INFO: [Vivado 12-1399] There are no top level ports directly connected to pins of cell 'system/v_tc', returning the pins matched for query '[get_ports s_axi_aclk]' of cell 'system/v_tc'. [C:/Design/v_tc.xdc:1]
Resolution: The get_ports call is being converted to a get_pins call as there is no direct connection to a top level port. This could be due to the insertion of IO Buffers between the top level terminal and cell pin. If the goal is to apply constraints that will migrate to top level ports it is required that IO Buffers manually be instanced. 

CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_max_delay constraint with option 'from'. [C:/Design/v_tc.xdc:1]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object.
WARNING: [Vivado 12-584] No ports matched 's_axi_aclk'. [C:/Design/v_tc.xdc:2]
WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of [get_ports s_axi_aclk]'. [C:/Design/v_tc.xdc:2]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [C:/Design/v_tc.xdc:2]


Vivado can contain hierarchical constraints, top level user constraints, and constraints that are delivered by an IP. These constraints can have dependencies which must be met in order to work correctly. One such is clock creation. Some IPs create clocks that other IPs or the top need, or some IPs require a clock to exist at the top level, to function correctly and not produce critical warnings.

If the necessary clock constraint is not being generated, then the IP/top will issue a CRITICAL WARNING as described above.

One way to find clocks in your design that are not being properly generated is to use the report_clock_networks command.  This command will list all the clocks in the design, including both the constrained and the unconstrained clocks.  You can then us this to find if the clock tied to your particular piece of IP needs to be properly constrained.

Another useful command is the report_clocks command.  This command will list all the clocks domains that constrained.  Another useful command is report_compile_order -constraints which will show which XDC files are being used for synthesis and implementation and in what order they are processed. If an IP XDC that is creating a clock comes after an IP XDC that needs the clock, this will help see the relationship.

Many times you can resolve issues of a missing clock coming from an IP by adding a constraint to your top level XDC timing constraints file. This could be the case when working with an XPS design where there are no XDC files present for some of the IPs that could be creating a clock, such as a GT.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54541 LogiCORE IP Video Timing Controller - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55248
Date Created 03/29/2013
Last Updated 08/06/2013
Status Active
Type General Article
  • Vivado Design Suite