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AR# 55293

2013.1 Vivado IP Flows - IP interface port names have been converted to use all lowercase characters in Vivado Design Suite 2013.1


To drive consistency across Xilinx IP, mixed case signal names have been changed to use all lowercase for all VHDL and Verilog-based Xilinx cores.

If you are creating a new IP core in Vivado Design Suite 2013.1, this should have no affect.

However, if you have an existing design (created in Vivado 2012.4 or ISE 14.4 or earlier tools) which instantiates an IP core, an interface port name mismatch may appear if the IP core is upgraded in Vivado Design Suite 2013.1 or later tools to use the latest IP version.

If there is a port mismatch, instantiating the design module must be changed to match the latest port names.

The links below provide specific details for IP affected by this change.


(Xilinx Answer 55006) - Aurora 8B/10B
(Xilinx Answer 55005) - Aurora 64B/66B
(Xilinx Answer 55001) - SelectIO Wizard
(Xilinx Answer 54997) - XADC Wizard
(Xilinx Answer 55084) - 7 Series PCIe
(Xilinx Answer 55085) - Virtex-7 PCIe Gen3
AR# 55293
Date Created 04/01/2013
Last Updated 11/06/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.1