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AR# 55297

Soft Error Mitigation (SEM) v3.5 - Setup time violations on Artix-7 and Zynq-7000 devices with 100 MHz ICAP clock

Description

When implementing the SEM IP targeting Artix or Zynq devices with a 100 MHz ICAP clock, setup time violations might occur between a RAMB18E1 in the controller and a register in the example design MON shim.

Solution

  1. Identify the failing path in the timing report.
  2. Add a constraint to overconstrain this path to 9.75 ns.
  3. Re-implement the design.
  4. Verify in the timing report that the design meets timing for 100 MHz performance.


Example

Source:               example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18 (RAM)

Destination:       example_mon/example_mon_fifo_tx/augend_3 (FF)

INST "example_controller/U0/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw1/fw1_1024x18" TPSYNC = RAM_SRC ;

TIMESPEC "TS_MAXDELAY" = FROM "RAM_SRC" TO FFS(*) 9750 ps ;

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44541 Soft Error Mitigation Controller - Release Notes and Known Issues for v1.1 to v3.4 N/A N/A
AR# 55297
Date Created 04/01/2013
Last Updated 04/03/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Zynq-7000
Tools
  • ISE Design Suite - 14.5
IP
  • Soft Error Mitigation