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AR# 55299

Soft Error Mitigation (SEM) v4.0 - Setup time violations on Artix-7 and Zynq-7000 devices with 100 MHz ICAP clock


When implementing the SEM IP targeting Artix or Zynq devices with a 100 MHz ICAP clock, setup time violations may occur between a RAMB18E1 in the controller and a register in the example design MON shim.


Identify the failing path in the timing report. Add a constraint to overconstrain this path to 9.75 ns. Re-implement the design. Verify in the timing report that the design meets timing for 100 MHz performance.

Example 2: Vivado
Source:                 example_controller/inst/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw0/fw0_1024x18/CLKBWRCLK
                          (rising edge-triggered cell RAMB18E1 clocked by clk)
Destination:            example_mon/example_mon_fifo_rx/augend_reg[5]/D
                          (rising edge-triggered cell FDRE clocked by clk)

set_max_delay -from [get_pins example_controller/inst/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw0/fw0_1024x18/CLKBWRCLK] -to [get_pins {example_mon/example_mon_fifo_rx/augend_reg[*]/D}] 9.750

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54642 Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55299
Date Created 04/01/2013
Last Updated 04/03/2013
Status Active
Type General Article
  • Zynq-7000
  • Artix-7
  • Vivado Design Suite - 2013.1
  • Soft Error Mitigation