UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55299

Soft Error Mitigation (SEM) v4.0 - Setup time violations on Artix-7 and Zynq-7000 devices with 100 MHz ICAP clock

Description

When implementing the SEM IP targeting Artix or Zynq devices with a 100 MHz ICAP clock, setup time violations may occur between a RAMB18E1 in the controller and a register in the example design MON shim.

Solution

Identify the failing path in the timing report. Add a constraint to overconstrain this path to 9.75 ns. Re-implement the design. Verify in the timing report that the design meets timing for 100 MHz performance.

Example 2: Vivado
Source:                 example_controller/inst/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw0/fw0_1024x18/CLKBWRCLK
                          (rising edge-triggered cell RAMB18E1 clocked by clk)
Destination:            example_mon/example_mon_fifo_rx/augend_reg[5]/D
                          (rising edge-triggered cell FDRE clocked by clk)

set_max_delay -from [get_pins example_controller/inst/wrapper_wrapper/genx7.wrapper_controller/controller_instrom/fw0/fw0_1024x18/CLKBWRCLK] -to [get_pins {example_mon/example_mon_fifo_rx/augend_reg[*]/D}] 9.750

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54642 Soft Error Mitigation IP Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55299
Date Created 04/01/2013
Last Updated 04/03/2013
Status Active
Type General Article
Devices
  • Zynq-7000
  • Artix-7
Tools
  • Vivado Design Suite - 2013.1
IP
  • Soft Error Mitigation