module test4 (clk,din,dout);parameter WIDTH = 20000;input clk;input [WIDTH-1:0] din;output reg [WIDTH-1:0] dout;generatebegin genvar i; for(i=0;i<WIDTH;i=i+1) begin always@(posedge clk) dout[i] <= din[i]; endend endgenerateendmodule
In the above sample code, the presence of the "for loop" construct encompassing the always statement has been observed as the prime reason for longer runtime.
To get around this long runtime behavior, modify the above sample Verilog code in the following manner to help reduce the runtime,
module test4 (clk,din,dout);
parameter WIDTH = 20000;
input clk;
input [WIDTH-1:0] din;
output reg [WIDTH-1:0] dout;
integer i;
generate
begin
always@(posedge clk)
begin
for(i=0;i<WIDTH;i=i+1)
dout[i] <= din[i];
end
end
endgenerate
endmodule
In the above sample code, moving the loop construct under the always statement helps reduce the longer run time. The above HDL coding style should be considered as an alternate effective solution by the user for reducing longer run times.