We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55320

14.x - Timing Analyzer - Viewing the Full Clocking Path Under a Period Constraint


In the period analysis we can see the clock skew reported. Is there any switch or setting in ISE which reports the complete clock path in period analysis like in offset analysis?


The Method to do this is shown below. The steps correspond to numbers in the images. The 'Stopwatch' example design was used here which can be found in:
File -> Open Example
(1) Double click the icon that looks like a stopwatch, shown below. This will Implement your design and run static Timing.
(2) Now select the .twx tab.
(3) When this tab is selected, you will see Timing appear in the top toolbar. Click Timing and then select Run Analysis.
(4) Change the analyze against field to User Defined Endpoints
(5) Select your endpoints and name your Analysis.
AR# 55320
Date Created 04/02/2013
Last Updated 04/02/2013
Status Active
Type General Article
  • FPGA Device Families
  • ISE