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AR# 55325

Zynq-7000 AP SoC, APU - Possible denial of service for coherent requests on an L1 cache line which is continuously written by a processor


A processor that performs a continuous stream of writes to the same L1 cache line might prevent another coherent processor or ACP to access the same cache line.


The following example describes one scenario that might trigger the issue:

  • CPU0 performs a read access to a coherent memory region, at address A.
  • CPU1 continues to execute a loop which solely contains write operations to the same cache line as address A.

In this example, the arbitration scheme of the Cortex-A9 MPCore always gives priority to the write requests from CPU1, preventing successful reads from CPU0. CPU0 is stalled and cannot make further progress.

Note that because CPU0 cannot complete its coherent read access, it cannot enter any debug-mode and cannot take any interrupt. If CPU1 also cannot be interrupted, for example if CPU1 has disabled its interrupts, or if all interrupts are routed to CPU0 only, this might cause a system livelock.

Impact: Minor. The denial of service on the other coherent agent might cause performance issues, or a possible system livelock. The system livelock might happen if it is not possible to interrupt the processor that is performing the continuous write stream.
Work-around: Break the continuous write stream, refer to the Work-around Details.
Configurations Affected: Systems that use two CPUs or one CPU and the ACP.
Device Revision(s) Affected: All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences
Third Party Errata: ARM Errata 791420

Work-around Details

To work around this issue, you can break the continuous write stream that causes the livelock by inserting a DMB instruction in the loop performing the write stream. If the software causing the write stream cannot be modified, the recommended work-around is to force CPU1 to regularly take an interrupt which acts as a watchdog. There are several ways this regular interrupt might be generated, and these can be system-specific. Interrupts generated by the local timer, global timer, or Performance Monitor Unit cycle counter overflow are possible candidates.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 55325
Date 05/15/2013
Status Active
Type Design Advisory
  • XA Zynq-7000
  • Zynq-7000