The ARM architecture specifies that the processor sets the Sticky Reset Status Bit, DBGPRSR[SR], to 1 when the non-debug logic of the processor is in reset state.
Instead, the processor sets this bit to 1 when the debug logic of the processor is in reset state.
This issue may cause two problems:
In both cases, the DBGPRSR.SR bit value might be corrupted which might prevent the debug logic from correctly detecting when the non-debug logic of the processor has been reset.
Systems that use the CPUs.
|Device Revision(s) Affected:||All. No plan to fix. Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences Answer Record.|
|Third Party Errata:||Arm Errata 799770|