UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55348

AXI Bridge for PCI Express v1.07.a - Interrupt Decode Register gets wrongly set when performing DMA with ASPM enabled in RC mode

Description

Version Found: v1.07.a / v2.0
Version Resolved and other Known Issues for v1.07.a/v2.0 : See (Xilinx Answer 44969) for v1.07.a and (Xilinx Answer 54646) for v2.0

When performing DMA with ASPM enabled with the core in RC mode, INTx bit of Interrupt Decode Register is set erroneously.

Solution

This is a known issue to be fixed in a future release of the core.

Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
04/03/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 55348
Date Created 04/03/2013
Last Updated 04/04/2013
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)