Version Found: v1.06.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)
When the AXI Bridge for PCI Express v1.06.a core is configured as x4Gen2 Root Complex for a Zynq device, the core does not send the corresponding CplD TLP in response to the read from the endpoint.
This is a known issue and will be fixed in the next release of the core.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
04/03/2013 - Initial release