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AR# 55377

2013.4 Vivado - Does the Vivado tool have an option to create an instantiation template for an existing HDL source?

Description

I would like to be able to select an existing Verilog or VHDL source file and automatically generate a valid instantiation template for the source.

Does the Vivado tool have an option to create an instantiation template for an existing HDL source?

Solution

Vivado 2013.4 does not have this capability.

However, in Vivado 2014.1 a TclAppStore option was added to enable this feature. 

See (Xilinx Answer 58023).
AR# 55377
Date Created 04/04/2013
Last Updated 03/10/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite