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AR# 55472

2013.1 Vivado Implementation - PhysOpt introduces VCC/GND conflicts on Block RAM pins due to Design Model issue

Description

A case has been seen where a design appeared to route successfully, but failed DRC when write_bitstream was run with resource conflicts and antennas reported on the VCC/GND nets:

Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 564659 :
# of nets not needing routing.......... : 170306 :
# of internally routed nets........ : 164198 :
# of nets with no loads............ : 6108 :
# of routable nets..................... : 394353 :
# of fully routed nets............. : 394351 :
# of nets with routing errors.......... : 2 :
# of nets with some unrouted pins.. : 1 :
# of nets with resource conflicts.. : 2 :
# of nets with antennas/islands.... : 1 :
------------------------------------------- : ----------- :

Solution

This problem was found to have been introduced during physopt_design due to a design model bug. A patch (attached) is available for use with 2013.1.

To install the patch:
- Create a patch directory (e.g. /tools/vivado_patches).
- Unzip the patch file in the patch directory while maintaining directory structure.
- setenv MYVIVADO  /tools/vivado_patches/vivado
- Start Vivado from the original install location

Attachments

Associated Attachments

Name File Size File Type
AR55472_designmodel_2013_1.zip 3 MB ZIP
AR# 55472
Date Created 04/09/2013
Last Updated 04/10/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Virtex-7
  • Kintex-7
Tools
  • Vivado Design Suite - 2013.1