UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 5553

1.5i Virtex Back Annotation - Simulation errors during physical back annotation (no .ngm) due to clock renaming by map.

Description

The symptom is the mapper produces a GCLKIOB comp whose name ("clock") collides with its output signal name. When ngdanno tries to name the top level port/signal after the IOB comp, the name collision is detected and that signal name is changed from "clock" to "clock_p". This causes the simulation problem.

signal CLOCK : STD_LOGIC;
^
**Error: vhdlan,1072 rphy.vhd(108):
Illegal redeclaration of CLOCK.
I => CLOCK_P,
^
**Error: vhdlan,575 rphy.vhd(809):
CLOCK_P is not declared.

Logical (with mapped.ngm) worked OK.

Solution

A fix for this problem is included in the 1.5i Service Pack 1. For details
on this Service Pack see http://www.xilinx.com/techdocs/5514.htm
AR# 5553
Date Created 02/02/1999
Last Updated 04/10/2000
Status Archive
Type General Article