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AR# 55538

MIG Virtex-6 - QDRII+ dbg_rd_stage1_cal connections incorrect in UG406

Description

Version Found: MIG Virtex-6 v3.92
Version Resolved: Not Resolved

The bits in Table 2-19: Read Stage 1 Debug Signal Map of the Virtex-6 FPGA Memory Interface Solutions User Guide v1.12 (UG406) are incorrect:
http://www.xilinx.com/support/documentation/ip_documentation/mig/v3_92/ug406.pdf

Solution

Table 2-19, of the Virtex-6 FPGA Memory Interface Solutions User Guide v1.12 (UG406), states the following:

 

In the phy_read_stage1_cal.vhd module, the correct connections are:

dbg_rd_stage1_cal(43) <= rei_captured;
dbg_rd_stage1_cal(146 downto 142) <= q_bit_load_sig;
dbg_rd_stage1_cal(147) <= q_bit_rst_sig;
dbg_rd_stage1_cal(153 downto 148) <= window_size;
dbg_rd_sage1_cal(216) <= rst_done;

Revision History
04/17/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
50642 MIG Virtex-6 and Spartan-6 v3.92 - Release Notes and Known Issues for ISE Design Suite 14.3 N/A N/A
AR# 55538
Date Created 04/12/2013
Last Updated 04/17/2013
Status Active
Type Known Issues
Devices
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Zynq-7000
IP
  • MIG 7 Series