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AR# 55539

Zynq-7000 AP SoC - Errata Work-around Solutions

Description

The Zynq-7000 production errata items, a subset of the items listed in (Xilinx Answer 47916), often include software work-around solutions implemented by Xilinx and the Linux community. 

Solution

The table below shows the status for each production errata item.

Note: Third Party Errata Items (for example, ARM) are listed in (Xilinx Answer 55518).

Legend for User Function columns:

  • ~ = not applicable
  • ^ = refer to alternate column
  • v = no workaround, considered a trivial issue
  • X = work-around in-place (or soon-to-be) or the issue is avoided
  • # = advisory for user to evaluate their situation
  • * = work-around not possible
  • <blank> = under investigation
User Guide column: This column contains notes about the work-around implementations.
Work-around Note column:
This column contains implementation-specific comments about the work-around or the reasons the work-around might not be applicable. The details of each errata item and possible work-around(s) are described in the individual Xilinx Answer Record.
Note: This information is subject to change as new Tools, Documentation, and other elements of the Zynq solution are released.
Production Errata Items:

Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
DDRC LPDDR2 Per-Bank Refresh Is Not Supported (Xilinx Answer 47580) ~ X X X X X ~ ~ ~ Xilinx tool does not provide Per-Bank Refresh option.
DDRC Read operations malfunction when they follow an MRW within 128 DDR clock cycles (Xilinx Answer 47581) ~ X X X X X ~ ~ ~ Xilinx tool sets reg_ddrc_t_mod to 512.
GigE Unicast and Broadcast Pause Frames Received by the Controller are not Filtered Out (Xilinx Answer 52025) ~ ~ ^ ^ ^ # ~ # ~ OS: Move to App to minimize performance impact.
App: under investigation.
Perf: under investigation.
GigE Back-off Time is more Aggressive than the Standard Requirement (Xilinx Answer 52026) ~ ~ ~ ~ ~ v ~ ~ ~ Work-around not feasible.
App: Minor protocol compliance issue.
GigE Packets up to 1536 bytes are Allowed with VLAN Tagging (Xilinx Answer 52027) ~ ~ v v v v ~ ~ ~ All: minor protocol compliance issue.
GigE Receive path Lock-Up might occur when a large number of Receive resource errors are generated (Xilinx Answer 52028) ~ ~ X X # ~ ~ # ~ Standalone: Work-around added in 14.5.
Linux: Work-around added in 14.5.
Other OS: Advisory.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
SDIO DMA Burst Transactions Alignment and Length Requirements (Xilinx Answer 47531) ~ ~ X X # # ~ ~ ~ Linux: All aligned to 4 bytes.
Standalone: All aligned to 4 bytes.
Other OS: Advisory.
App Layer: Advisory.
SDIO Software Reset Sequence for SDIO can Hang the Interconnect (Xilinx Answer 47532) ~ ~ X X # # ~ ~ ~ Linux: All have correct sequence.
Standalone: All have correct sequence.
Other OS: Advisory.
App Layer: Advisory.
SDIO Second CMD12 can be Issued if Auto CMD12 is Enabled (Xilinx Answer 47533) ~ ~ ^ ^ ^ # ~ ~ ~ App Layer: Avoid sequence in SD stack.
SDIO ADMA2 Mode Fails to Release Properly when Abort CMD is Issued (Xilinx Answer 47534) ~ ~ ^ ^ ^ # ~ ~ ~ App Layer: Avoid sequence in SD stack.
SDIO Transfer Complete Asserts before Completing Busy due to CMD13 (Xilinx Answer 47535) ~ ~ ^ ^ ^ # ~ ~ ~ App Layer: Avoid sequence in SD stack.
SDIO CMD13 not Handled Properly when CMD19 is in Progress (Xilinx Answer 47536) ~ ~ ^ ^ ^ # ~ ~ ~ App Layer: Avoid sequence in SD stack.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
SMC NAND with ECC might not De-assert CS between Data Transactions (Xilinx Answer 47517) ~ ~ X X # # ~ ~ ~ Linux and Standalone: Column change commands never used.
Other OS: Advisory.
App Layer: Impact may be device-specific.
SMC Potential SRAM/NOR Data Error (Xilinx Answer 47518) ~ ~ ~ ~ ~ ~ under investigation
SMC
NAND ECC Status Register can Incorrectly Report a Failure for One Clock Cycle (Xilinx Answer 47520) ~ ~ X X # ~ ~ ~ ~ Linux and Standalone: Sequence is always avoided.
Other OS: Advisory, see (Xilinx Answer 47520).
SMC SMC Parallel (SRAM/NOR) Interface Does Not Correctly Assert CS0 For 64 MB Memories (Xilinx Answer 61637) ~ X X X X X ~ ~ ~ Solution is provided in (Xilinx Answer 60848)
SMC SMC Parallel (SRAM/NOR) Interface Address Bit 25 Is Inverted For 64 MB Memories (Xilinx Answer 61638) ~ X X X X X ~ ~ ~ Solution is provided in (Xilinx Answer 60848)
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
Timers Global Timer can Send Two Interrupts for the Same Event (Xilinx Answer 47545) ARM 740657 ~ ~ ~ # ~ ~ ~ ~ Linux and Standalone: Global Timer is not used.
Other OS: Advisory, see (Xilinx Answer 47545).
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
USB Device Mode Does not Generate a Port Change Interrupt when Session is no Longer Valid (Xilinx Answer 47538) ~ ~ X X # ~ ~ ~ ~ Linux: Device Mode: Work-around added in 14.5.
Linux: OTG: Work-around not planned.
Standalone: Work-around not planned.
Other OS: Advisory.
Soln: VBus discharge is detected via end of B session.
USB Suspend Bit is Asserted before the Port Enters the Suspend State (Xilinx Answer 47539) ~ ~ ~ ~ ~ # ~ ~ ~ App Layer: Delay in the application is greater than the suspend bit delay.
USB First SOF after a Software Reset can be Corrupted (Xilinx Answer 47540) ~ ~ ~ ~ ~ ~ ~ ~ ~ Controller hardware will ignore the SOF packet.
USB In HS Host Mode, NYET Decrements NAK Counter (Xilinx Answer 47541) ~ ~ ~ ~ ~ ~ ~ Minor, work-around not planned, see (Xilinx Answer 47541).
USB
ULPI Viewport does not Work with Extended Addresses (Xilinx Answer 47543) ~ ~ ~ ~ ~ * ~ ~ ~ Work-around not possible.
I2C Fast Mode running faster than 384kHz violates tLOW; STA timing requirement (Xilinx Answer 60693) ~ ~ ~ ~ ~ ~ ~ ~ ~ See work-around in (Xilinx Answer 60693)
I2C 60694 - Zynq-7000 AP SoC, I2C - Fast Mode running faster than 384 kHz violates tBUF; STA timing requirement (Xilinx Answer 60694) ~ ~ ~ ~ ~ ~ ~ ~ ~ See work-around in (Xilinx Answer 60694)
I2C I2C Missing Arbitration on Repeated Start (Xilinx Answer 60695) ~ ~ X X ~ ~ ~ ~ ~ Standalone: Work-around added in 2014.4
Linux: Work-around added in 2015.1
I2C Standard Mode running faster than 90 kHz violates tHD; STA timing requirement (Xilinx Answer 59366) ~ ~ ~ ~ ~ ~ ~ ~ ~ See work-around in (Xilinx Answer 59366)
I2C I2C Master Generates Invalid Read Transactions (Xilinx Answer 61664) ~ ~ X X ~ ~ ~ ~ ~ Standalone: Work-around added in 2015.1
Linux: Work-around added in 2015.1
I2C Missing I2C Master Completion Interrupt (Xilinx Answer 61665) ~ ~ X X ~ ~ ~ ~ ~ Standalone: Work-around added in 2014.4
Linux: Work-around added in 2015.1
I2C Missing Glitch Filter Implementation in Zynq PS I2C Controller (Xilinx Answer 61861) ~ ~ ~ ~ ~ ~ ~ ~ ~ PCB design guide will be updated
I2C I2C Transaction Corruption In Slave Receiver Mode (Xilinx Answer 63025) ~ ~ ~ ~ ~ ~ ~ ~ ~ See work-around in (Xilinx Answer 63025)
I2C PS I2C Slave Monitor Mode Can Lock the I2C Bus (Xilinx Answer 63245) ~ ~ ~ ~ ~ ~ ~ ~ ~ See work-around in (Xilinx Answer 63245)
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
APU Processor might miss Watchpoint on Second Part of Unaligned Access Crossing Page Boundary (Xilinx Answer 47546) ARM 751476 ~ ~ ~ ~ ~ v ~ ~ Debug: Advisory, see work-around in (Xilinx Answer 47546).
APU Following an ASID Switch, Faulty MMU Translations can Occur (Xilinx Answer 47547) ARM 754322 ~ X ~ # ~ ~ ~ ~ Only applies to systems using address translation.
Linux: Work-around enabled by default in 14.6/2013.2.
Linux Note: Refer to CONFIG_ARM_ERRATA_754322.
Other OS: Advisory.
APU Ordering of Read Accesses to the Same Memory Location Might not be Ensured (Xilinx Answer 47548) ARM 761319 ^ ^ ^ ^ ~ ~ ~ Compiler: Compiler solution planned for 2013.4
Others: Advisory.
APU System Deadlock can occur in SMP Mode when the Same Cache Line is Accessed by Both CPUs and the ACP (Xilinx Answer 47549) ARM 761320 ~ X ~ # ~ ~ ~ ~ Only applies to SMP Mode.
Linux: Work-around to be enabled by default in future release.
Linux Note: Refer to CONFIG_ARM_ERRATA_742230.
Other OS: Advisory.
APU Cache Line Maintenance Operations by MVA might not Succeed on an Inner Shareable Memory Region (Xilinx Answer 47550) ARM 764369 ~ X ~ # ~ ~ ~ ~ Only applicable in SMP mode.
Linux: Work-around enabled by default in 14.6/2013.2.
Linux Note: Refer to CONFIG_ARM_ERRATA_764369.
Other OS: Advisory.
Soln: A DSB is added before the cache maintenance operations.
APU ISB Instruction is Counted in Performance Monitor Events 0x0C and 0x0D (Xilinx Answer 47551) ARM 725631 ~ ~ ~ ~ ~ ~ ~ v PMU: Minor impact. Work-around not possible.
APU ARM MainID Registers are not Aliased to Debug Interface on APB (Xilinx Answer 47552) ARM 729817 ~ ~ ~ ~ ~ v ~ ~ Debug: MainID register is not accessed by debugger.
APU ARM Debug Execution Stalls when an Instruction is Written to the ITR Following an Aborted Load/Store (Xilinx Answer 47553) ARM 729818 ~ ~ ~ ~ ~ X ~ ~ Debug: Work-around in debugger.
Soln: Debuggers implement instruction coalescing and the issue is currently not seen.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
APU Debug Program Counter Sampling (DBGPCSR) Register Format is Incorrect (Xilinx Answer 47554) ARM 751471 ~ ~ ~ ~ ~ X ~ ~ Debug: Work-around in debugger.
Soln: Debugger reads the DBGPCSR register and the issue is currently not seen.
APU Imprecise Abort can be Reported Twice on Non-Cacheable Reads (Xilinx Answer 47555) ARM 752519 ~ ~ ~ ~ ~ ~ ~ ~ Work-around not required.
Note: An abort is an unrecoverable system error.
APU Repeated CPU Store Instructions within same Cache Line can Delay Visibility of the Store (Xilinx Answer 47556) ARM 754323 ^ # # # ~ ~ ~ ~ Work-around not planned.
APU Sticky Pipeline Advance Bit is not Supported (Xilinx Answer 47557) ARM 756421 ~ ~ ~ ~ ~ v ~ ~ Debug: feature not used.
APU Unallocated Memory Hint Instruction can Generate an Undefined Exception Instead of Being Treated as a NOP (Xilinx Answer 47558) ARM 757119 v ^ ^ ^ ~ ~ ~ ~ Work-around not planned.
APU MRC and MCR Instructions are not Counted in Event 0x68 (Xilinx Answer 47559) ARM 761321 ~ ~ ~ ~ ~ ~ ~ v PMU: Minor impact.
APU Read Accesses to a DBGPRSR or DBGOSLSR Register by the DAP Controller can Generate an Unexpected Undefined Exception (Xilinx Answer 47560) ARM 764319 ~ ~ ~ ~ ~ # ~ ~ Debug: Advisory.
APU L2-Cache High Priority for SO and Dev Reads Feature might Cause QoS Issues to Cacheable Read Transactions (Xilinx Answer) 47561 ARM 729815 ~ ~ ~ v ~ ~ ~ ~ All: Feature not used.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
APU L2-Cache A Continuous Write Flow can Stall a Read Targeting the Same Memory Area (Xilinx Answer 47562) ARM 754670 v v v v v ~ v ~ No work-around.
Compiler: under investigation.
OS: under investigation.
APU L2 Cache Controller can Prefetch Across 4 KB Boundary with Offset set to 23 (Xilinx Answer 47563) ARM 765569 ~ X X # ~ ~ ~ ~ Linux: Avoided in all releases.
Standalone: Avoided in all releases.
Other OS: Advisory.
APU PLD Instructions might Allocate even in a Disabled Data Cache (Xilinx Answer 47584) ARM 771221 ~ X X v ~ ~ # ~ Linux: Data cache is enabled by default.
Standalone: Data cache is enabled by default.
Other OS: Advisory when disabling data cache.
App: Advisory when disabling data cache.
Perf: Impacted when data cache is disabled.
APU Visibility of Debug Enable Access Rights to Enable/Disable Tracing is not Ensured by an ISB Instruction (Xilinx Answer 47585) ARM 771224 ~ ~ ~ ~ ~ v ~ ~ Debug: Advisory.
APU Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor, can Lead to Livelock (Xilinx Answer 47586) ARM 771225 v ~ ~ v ~ ~ v ~ Compiler: Branch prediction is enabled by default, user must take care when disabling branch prediction.
APU Parity Errors on BTAC and GHB are Always Reported Regardless of the Parity Enable Bit Setting (Xilinx Answer 47587) ARM 771223 ~ v v v ~ ~ ~ ~ Work-around not planned, refer to (Xilinx Answer 47587).
APU Strongly Ordered Write followed by LDREX might Deadlock Processor (Xilinx Answer 51122) ARM 782772 ~ v v v ~ ~ ~ ~ Compiler: LDREX is not compiler driven.
OS: The issue has not been seen.
APU A data cache maintenance operation which aborts, followed by an ISB, without any DSB in-between, might lead to deadlock (Xilinx Answer 52031) ARM 775420 ~ X X # ~ ~ ~ ~ Linux: Work-around enabled by default in 14.6/2013.2.
Linux Note: Refer to CONFIG_ARM_ERRATA_775420.
Standalone: Work-around added in 14.6/2013.2.
Other OS: Advisory.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
APU A short loop including a DMB instruction might cause a denial of service on another processor which executes a CP15 broadcast operation (Xilinx Answer 52032) ARM 794072 ~ X ~ v ~ ~ ~ ~ Applies to SMP Mode with short loop code.
Linux: Work-around enabled by default in 14.6/2013.2.
Linux Note: Refer to CONFIG_ARM_ERRATA_742230.
Other OS: Advisory.
APU Speculative instruction fetches with MMU disabled might not comply with architectural requirements (Xilinx Answer 52033) ARM 794073 ~ ~ X # ~ ~ ~ ~ Linux: MMU always assumed to be enabled.
Standalone: Advisory.
Other OS: Advisory.
APU A write request to Uncacheable, Shareable normal memory region might be executed twice, possibly causing a software synchronization issue (Xilinx Answer 52034) ARM 794074 ~ X ~ # ~ ~ ~ ~ Applies to SMP mode.
Linux: Workaround using STREX implemented.
Other OS: Advisory.
App: Advisory.
APU Updating a translation entry to move a page mapping might erroneously cause an unexpected translation fault (Xilinx Answer 52035) ARM 782773 ~ v ~ v ~ ~ ~ ~ Linux: Work-around not planned.
Standalone: Not applicable with static MMU translation.
Other OS: Advisory.
APU Cortex-A9 performance monitor event 0x0A (exception return) might count twice the LDM PC ^ instructions with base address register write-back (Xilinx Answer 52036) ARM 775419 ~ ~ ~ ~ ~ ~ ~ v PMU: Minor impact.
APU A spurious event 0x63, STREX passed, can be reported on an LDREX instruction that is preceded by a write to Strongly Ordered memory region (Xilinx Answer 55018) ARM 782774 ~ ~ ~ ~ ~ ~ ~ v PMU: Minor impact.
APU Possible denial of service for coherent requests on an L1 cache line which is continuously written by a processor (Xilinx Answer 55325) ARM 791420 ~ v v v ~ ~ ~ ~ Linux: Advisory.
Standalone: Advisory.
Other OS: Advisory.
APU A branch-to-self instruction in the last L1 cache line of a page might cause a denial of service (Xilinx Answer 55326) ARM 799769 ~ v v v ~ ~ ~ ~ Linux: Advisory.
Standalone: Advisory.
Other OS: Advisory.
Device Module Description (Xilinx Answer) Third Party Errata Ref GNU C/C++ Linux Stand alone Other OS App Layer Debug Perf. PMU User Notes
APU Write Context ID event in a CPU is updated on read access (Xilinx Answer 55327) ARM 795769 ~ ~ ~ ~ ~ ~ ~ v PMU: Minor impact.
APU DBGPRSR Sticky Reset status bit is set to 1 by the CPU debug reset instead of by the CPU non-debug reset (Xilinx Answer 55328) ARM 799770 ~ ~ ~ ~ ~ v ~ ~ Debug: under investigation
AR# 55539
Date Created 04/14/2013
Last Updated 01/13/2016
Status Active
Type Design Advisory
Devices
  • XA Zynq-7000
  • Zynq-7000
  • Zynq-7000Q