We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55602

MIG 7 Series QDRII+ - Data failures can occur when Fixed Latency mode is enabled


Version Found: v1.7
Version Resolved: See (Xilinx Answer 45195) and (Xilinx Answer 54025)

Data failures can occur when using the MIG 7 Series QDRII+ design with Fixed Latency mode enabled. This can occur when the read latency for one or more data byte lanes determined during calibration is longer than the specified Fixed Latency (PHY_LATENCY parameter) and the others are not.


When this condition occurs, error_adj_latency will assert, but calibration will still complete and then data failures will occur. The type of data failure seen will not be bit corruption, but offset read data returned. To work around this issue, the user can disable Fixed Latency Mode or increase the PHY_LATENCY to a value larger than the longest actual latency determined during calibration. To force calibration to fail when error_adj_latency is asserted, the following lines of code can be added to mig_7series_v1_9_qdr_rld_phy_read_stage2.v between line 819 and 820:

Line 817      always @(posedge clk) begin
Line 818        if (rst_clk)
Line 819          cal_stage2_done <= #TCQ 0;
                       else if (error_adj_latency)
                          cal_stage2_done <= #TCQ 0;
Line 820        else
Line 821          cal_stage2_done <= #TCQ |lat_adj_done;
Line 822      end

Revision History
05/09/2013 - Added RTL fix 
05/02/2013 - Initial release


Linked Answer Records

Master Answer Records

AR# 55602
Date Created 04/18/2013
Last Updated 05/09/2013
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series