We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55622

2013.1 Vivado Implementation - Placer incorrectly combines RAM128X1S with SRL16E in same slice leading to DRC error


A case has been seen where the placer was incorrectly combining a RAM128X1S with and SRL16E which resulted in the following DRC error:

ERROR: [Drc 23-20] Rule violation (PDRC-77) SLICEM_RamSame_D6 - Invalid programming for cell SLICE_X68Y182 with RAMMODE programming and WA7 input pin used for cell D6. This programming requires all the SLICEM implemented luts to be programmed the same type of RAM and WA7 pin..


You can work around this issue by creating an XDC macro that forces the placement of the RAM128X1S and SRL16E in adjacent sites ensuring that they will not be placed in the same site:

create_macro XLNX_WA_1
update_macro XLNX_WA_1 {/cell/name/1 X0Y0 /cell/name/2 X0Y1}

The cells could be LOC constrained apart, however this macro solution is better because it gives the placer freedom to place the macro anywhere it deems necessary.

The placement error described in this answer record is fixed in the 2013.2 release.

AR# 55622
Date 09/12/2014
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2013.1
Page Bookmarked