We do not give trace length data, but rather give the delay in time, as it is the most accurate way to estimate true package delay.
1) Open any design in Vivado, either RTL, Netlist or Implemented. Then select Export > I/O Ports > CSV.
You will see all of the min and max package delays for each pin.
The min/max trace delays are also displayed in the Package Pins window for every package pin within two separate columns.
Similarly you can select File->Export I/O ports to get a CSV type spreadsheet with the delays included.
2) If there is no project you can use the following Tcl commands:
link_design -part <part_number>
link_design -part xc7k410tffg900-2