Attached is a simple XPS/SDK design with the AXI Exerciser core connected to an HP port.
Control is provided through a GP port to the core.
The example code generates single and burst cycles to the HP port.
The cycles can then be viewed using ChipScope Pro Analyzer.
It is a useful example to show AXI cycles taking place in the PL to the PS for customers designing their own AXI masters, or to get an idea on latencies based on different type of cycles.
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