Version Resolved and other Known Issues: See (Xilinx Answer 54646)
When using the AXI Bridge for PCI Express core, designs might fail to meet timing on the following devices:
For Vivado 2015.3
In case of timing violation, set opt_design to "Explore Sequential Area".
For Vivado 2014.4
In cases of timing violations with the default implementation strategy, re-implement the design by selecting the "performance_ExplorePostRoutePhysOpt" implementation strategy.
For Vivado 2013.4 - Vivado 2014.3
To eliminate timing violations, set the properties below:
For x1g1_128bit configuration:
For x1g2_128bit configuration:
For x4g2_128bit configuration:
Note: "Version Found" refers to the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|10/06/2015||Updated for 2015.3|
|03/19/2015||Updated for smaller Zynq devices|
|01/08/2015||Added update for 2014.4|
|10/02/2014||Updated for v2.5|
|4/16/2014||Updated with Workaround|