We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55717

2013.1 Vivado FIFO Generator v10.0 - Patch update for FIFO Generator v10.0 to address the issue in core generated XDC for synchronous Distributed RAM based FIFO


Constraints generated by FIFO Generator v10.0 in XDC file incorrectly sets the false path on output registers for synchronous Distributed RAM FIFO. This causes design failing in hardware

Here is the constraint mention in generated xdc file:

set wr_clock       [get_clocks -of_objects [get_ports clk\]]

# Ignore paths from the write clock to the read data registers for Synchronous Distributed RAM based FIFO

set_false_path -from $wr_clock -to [get_cells inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[*\]]


This is a known issue in the Vivado 2013.1 generated XDC file.

To resolve this issue, you must install the attached patch over your Vivado Design Suite 2013.1 installation.

To install the patch, unzip the contents of the ZIP file to the root directory of your Vivado tool installation. Installation instructions are available in the "readme" file that is attached.


Associated Attachments

AR# 55717
Date 11/05/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.1
  • FIFO Generator
Page Bookmarked