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AR# 5572

CPLD XC9500 CoolRunner-II - How do I internally source global signals (clock, reset, output enable)?

Description

It is sometimes necessary to internally generate a signal and route it to a global signal.

However, there is no logic available between the global pin and the global buffers.

Can I do this without having to route the signal out of the chip and then back to the proper global pin?

Solution

Use the following constraint on the signal that you wish to place on a global net: 

 

BUFG=CLK|OE|SR; 

 

WARNING: For the XC9500/XL/XV and CoolRunner-II families, this constraint makes the global pin active. 


Be sure that a global pin used in this way is unconnected on the board. 

 

For example: 

 

To place an internally generated node on a global clock buffer, enter the following in your UCF: 

 

net my_net BUFG=CLK; 

 

Replace "CLK" with "OE" for a global output enable or "SR" for a global set/reset. 

 

This solution does not apply to the CoolRunner XPLA3 device because the global clock pins do not support bi-directional logic. 


Additionally, XPLA3 devices do not have global set/reset/output enable pins. 

 

For other common CPLD questions, refer to the CPLD FAQ: (Xilinx Answer 24167)

Attachments

Associated Attachments

AR# 5572
Date Created 08/21/2007
Last Updated 06/27/2014
Status Active
Type General Article
Devices
  • 9500
  • 9500XL
  • 9500XL IQ
  • More
  • 9500XL XA
  • 9500XV
  • CoolRunner-II
  • CoolRunner-II XA
  • Less