UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55739

LogiCORE IP Serial RapidIO Gen2 v2.0 - No packets transferred in example design simulation

Description

Version Found: 2.0
Version Resolved and other Known Issues for v2.0 core: See (Xilinx Answer 54648)

When simulating the LogiCORE IP Serial RapidIO Gen2 v2.0 example design, the simulator reports 'Test Passed,' but no packets are transferred between the core and the test bench.

Solution

This is a known issue to be fixed in the next release of the core.

To work around the issue in this release of the core, install the SRIO Gen2 v2.0 Rev1 patch that is available in (Xilinx Answer 55737).

Revision History
05/02/2013 - Initial release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54648 LogiCORE IP Serial RapidIO Gen2 Core - Release Notes and Known Issues for Vivado 2013.1 and newer tools N/A N/A
AR# 55739
Date Created 04/26/2013
Last Updated 11/05/2013
Status Active
Type Known Issues
IP
  • Serial RapidIO