We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55748

14.5 - PAR/Timing Report - What is the difference between Direct and Derivative?


In the timing report it lists both Direct and Derivative Paths. What is the difference between the two?


Below is an example output from the PAR report:

A derivative is a path clocked by a child clocking constraint derived from a given period constraint. A direct is a path directly clocked by a given period constraint.

Applied to an example, consider the circuit below. Note that this circuit corresponds to the table above.

We know that the actual period is applied at the "Clk" pin to the FPGA (TS_Clk). Since that path does not clock any logic (it only drives the MMCM), it has no direct paths analyzed. It does however have derivative paths being analyzed due to the 'derived period constraint' spanning out from the MMCM (TS_CLKOUT0).

On the other hand, the MMCM has no derivative paths, as the period spanning from its output does not go through any additional transformation. Since it directly clocks logic, the table shows direct paths being analyzed.

AR# 55748
Date 04/30/2013
Status Active
Type General Article
  • FPGA Device Families
  • ISE
Page Bookmarked