We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55756

14.x Schematic - RTL Viewer fails to show top level port connection to component blocks


My design has a port bus signal (e.g. test[3:0]) connected in the RTL code.   However, when I open the RTL Viewer, this port shows no connections to any elements in the design.
When trying to expand the port (double-clicking on its net), it expands to different elements, but shows no connection between them. Continuing to double-click shows more elements, but no connections.

When viewing Technology Schematic, all connections are visible to that top level port.

Viewing the project in PlanAhead tool, the RTL Design View does show all connections.


In ISE Design Suite 14.1, there were frequent reports of I/O ports drawn as hanging ports in the RTL viewer.  The issue has been linked to bus block consolidation (multiple bus-blocks being drawn as a single bus-block, at which point the bus signal consolidation is getting confused).

In ISE Design Suite 14.2, the main known cause of this issue was fixed.  However, there are still occasional instances where a port I/O is drawn unconnected.

Note that if you toggle bit-bus mode, you will see pins and signals connected properly.

The Technology Viewer and PlanAhead Schematic View have both been shown to render the I/O connections correctly when tested with designs exhibiting this issue.

AR# 55756
Date 05/09/2013
Status Active
Type Known Issues
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14
Page Bookmarked