If the Use Embedded Register option is enabled for the System Generator FIFO, TO_FIFO, FROM_FIFO blocks, the simulation shows incorrect latency (i.e., the latency through the core is there regardless of this option being enabled or not).
Why is this occurring?
This is a known issue in System Generator for the FIFO, TO_FIFO, and FROM_FIFO blocks. This is fixed in the ISE System Generator 14.6 and Vivado System Generator 2013.2 tools.
For now, it should be noted that this is a System Generator simulation issue only; the HDL netlist is correct and the System Generator project can be run in the ISE or Vivado simulators without issue.
It can also be seen that the DO_REG attribute is correctly set when this parameter is selected.