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AR# 55828

System Generator - The TO_FIFO and FROM_FIFO %FULL flags do not always run accurately in System Generator simulation


It has been found that the %FULL flags in the TO_FIFO and FROM_FIFO blocks are not always simulated correctly in the System Generator simulation environment.


This is a simulation only issue and the problem does not occur on hardware.

It is planned to be fixed in ISE System Generator 14.6 and Vivado System Generator 2013.2.
AR# 55828
Date Created 05/02/2013
Last Updated 08/19/2014
Status Active
Type General Article
  • System Generator for DSP - 14.1
  • System Generator for DSP - 14.2
  • System Generator for DSP - 14.3
  • More
  • System Generator for DSP - 14.4
  • System Generator for DSP - 14.5
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2012.4
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.2
  • Vivado Design Suite - 2012.1
  • Less