We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55867

CORE Generator - Fail to generate 3GPP_LTE_MIMO_DECODER 1.0 core on Windows 64 bit system


I try to generate 3GPP_LTE_MIMO_DECODER core on Windows (Win XP or Win7) and get the following error message:

ERROR:encore:132 - Failed to generate unit:
End of process call...
ERROR:Xst:2647 - Failed to run core generator for <lte_mimo_dec_v2_0_bvt27770_0_lte_3gpp_mimo_decoder_v2_0_xst_1_blk_mem_gen_v4_1_1> macro.

How to solve the issue?


This issue can be linked to the 260 bit command line limit on Windows Operating Systems.  If the user looks into the xst.log file created for the IP core, they would see a message similar to the following.

Release 12.4 - generatecore $Revision: $ (nt64)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Last:0 Text:Warning: EDIF Netlist being generated
XSTHandler: XST: HDL Parsing
ERROR: Exception caught when running XST synthesis!
Exception in thread "main" java.lang.RuntimeException: XST has returned an
error: ERROR:HDLCompiler:0 - "Unknown" Line 0: cannot open file
_v4_1/blk_mem_gen_v4_1.vdbl" for writing

The 3GPP_LTE_MIMO_DECODER 2.1 IP has been enhanced to allow a longer initial path.

To work around the issue when generating a 3GPP_LTE_MIMO_DECODER 1.0 IP core:

  • Choose a shorter IP core project path
  • Use a Linux operating system.
AR# 55867
Date 06/24/2013
Status Active
Type General Article
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14
  • 3GPP LTE MIMO Decoder
Page Bookmarked