UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 55878

14.1 PlanAhead - Critical Error message of "Create run with incorrect top" should not have an "Ignore" checkbox

Description

In a PlanAhead project, I generate an IP (such as block RAM) and set the new generated IP as top level. When I try to create a new run in the design, in the last steps PlanAhead pops up a critical warning that there is no Verilog and VHDL sources found in the project. This is true since the IP core composite file is selected as top. However, there is a "Don't show this dialog again" checkbox on the Critical warning message. If I select this, the Create Runs operation can then continue by selecting "Finish".

Solution

This critical warning message should not have an "Ignore" checkbox on Create Run with an incorrect top.

In the Vivado 2012.2 and PlanAhead 14.2 tools, this issue has become obsolete as the XCI/XCO file cannot be set to the top level. The "Set as Top" button in the right-clicking menu for the XCO/XCI file is grayed out.
AR# 55878
Date Created 05/06/2013
Last Updated 10/04/2013
Status Active
Type Known Issues
Tools
  • PlanAhead - 13