We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 55905

2013.1 Vivado Timing - The auto-generated clock name changing during optimization causes the timing info in the project summary to be inconsistent with the user-generated timing summary report


After implementation, the post-implementation timing result in the project summary is inconsistent with the timing result from the report_timing_summary run by user. What is the problem?


By comparing the two timing summary report we know that the discrepancy comes from the analysis between two inter clocks. The two clocks have been defined as asynchronous by set_clock_groups in the XDC. But the auto-generated timing summary report from which the timing information in project summary is extracted still has the inter clocks analysis between the two clocks.

Root cause:

One of the two clocks is the MMCM output clock which is defined with an auto-generated clock name. Its name is changed due to optimization during implementation. The auto-generated report_timing_summary honors the name before changing, so it misses the set_clock_groups constraint on this clock.


This is fixed in 2013.2, so that once names are assigned by the tool, they will not change as netlist optimizations occur.

In 2013.1, use the either of the following solutions.

  1. Use a unique clock net name on the port connection of the MMCM instances. Vivado tool uses the port connection name to define the auto-generated clock. Having duplicated port connection names causes Vivado tool to rename the clock, and that may cause a naming change due to optimization in implementation.
  2. Avoid using the auto-generated clock names in constraints. It is better for user to define the clock names explicitly or use appropriate Tcl commands to specify the objects. See following examples.



set clk0 [get_clocks of [get_pins {mmcm1_inst/MMCME2_BASE_inst1/CLKOUT0}] ];
set clk2 [get_clocks of [get_pins {mmcm2_inst/MMCME2_BASE_inst2/CLKOUT2}] ];
set_clock_groups -asynchronous -group [get_clocks $clk0] -group [get_clocks $clk2];


set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks clkin1 ] -group [get_clocks -include_generated_clocks clkin2]
AR# 55905
Date 08/06/2013
Status Active
Type General Article
  • Vivado Design Suite - 2013.1