Version Found: v1.9
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
If generating the 7 series Integrated Block for PCI Express v1.9 core for Artix-7 devices and implementing in ISE 14.5 design tools, the design might not meet timing.
This is a known issue and is not scheduled to be fixed.
It is advised that you generate and implement Artix-7 FPGA designs in the Vivado design suite. There is no such timing issues when implemented in Vivado tools.
Note: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
05/23/2013 - Initial release