Description

I have one period requirement that is 20 ms. The tool reports a timing violation of the component switching limit of the slice clock input, which seems to be an error in calculation.

Component Switching Limit Checks: TS_clk_20ms = PERIOD TIMEGRP "clk_20ms" 20000000 ns HIGH 50% INPUT_JITTER 0.3 
ns; 
-------------------------------------------------------------------------------- 
Slack: -2147484.123ns (period - min period limit) 
Period: -2147483.648ns 
Min period limit: 0.475ns (2105.263MHz) (Tcp) 
Physical resource: rst2_r/CLK 
Logical resource: rst2_reg/CK 
Location pin: SLICE_X20Y29.CLK 
Clock network: clk_20ms 

Solution

The upper period value limit for timing is 2 ms, so the period requirement of 20 ms has exceeded the timing engine limit. If you reduce the period to 2 ms, then the analysis will be correct. 

This error can be safely ignored.