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AR# 55948

14.x Timing - Component Switching Limit violation when period value is longer than 2 ms

Description

I have one period requirement that is 20 ms. The tool reports a timing violation of the component switching limit of the slice clock input, which seems to be an error in calculation.

Component Switching Limit Checks: TS_clk_20ms = PERIOD TIMEGRP "clk_20ms" 20000000 ns HIGH 50% INPUT_JITTER 0.3 
ns;
--------------------------------------------------------------------------------
Slack: -2147484.123ns (period - min period limit)
Period: -2147483.648ns
Min period limit: 0.475ns (2105.263MHz) (Tcp)
Physical resource: rst2_r/CLK
Logical resource: rst2_reg/CK
Location pin: SLICE_X20Y29.CLK
Clock network: clk_20ms 

Solution

The upper period value limit for timing is 2 ms, so the period requirement of 20 ms has exceeded the timing engine limit. If you reduce the period to 2 ms, then the analysis will be correct. 

This error can be safely ignored.

AR# 55948
Date Created 05/09/2013
Last Updated 08/06/2013
Status Active
Type General Article
Tools
  • ISE
  • ISE Design Suite - 13
  • ISE Design Suite - 14