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AR# 55952

CPRI v7.0 - MMCM Output Clock Changes

Description

Due to the optimization behavior of the vivado synthesis tool, changes must be made to the component_name_tx_clk_gen.vhd file in the synth/gtx_and_clocks directory.

Solution

The following lines should be removed:

-- Select between the 6 possible output clocks.
-- As the mmcm_output_select input is a static
-- signal the tools should optimize this to a
-- single wire.
clkout0 <= clkout1_i when mmcm_output_select = "001" else
           clkout2_i when mmcm_output_select = "010" else
           clkout3_i when mmcm_output_select = "011" else
           clkout4_i when mmcm_output_select = "100" else
           clkout5_i when mmcm_output_select = "101" else
           clkout6_i when mmcm_output_select = "110" else
           clkout0_i;
 

The clock should then be connected manually to the required MMCM clock output. As an example, if mmcm_output_select = 000, the above lines are replaced by:

clkout0 <= clkout0_i;

In Artix-7 FPGA implementations, the clkout1 signal should be manually connected in the same way.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54473 LogiCORE IP CPRI Core - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 55952
Date Created 05/10/2013
Last Updated 12/03/2013
Status Active
Type General Article
IP
  • CPRI