Why do I see write failures on the AXI4-Lite bus, when the AXI4-Stream clock is at a different frequency than the AXI4-Lite interface clock?
This usually happens when the clocks are not an even multiple of each other, and the AXI4-Steam clock is faster than the AXI4-Lite clock.
This is a known issue in the Video Timing core that can also affect other Video IP, and it is recommended that all designs using the Video IP listed below with an AXI4-Lite interface should be updated to one of the versions listed below.
This issue has been resolved in the Video Timing Controller v5.01.a Rev 3 pCore or later patch for ISE Design Suite. Installing this patch will address this for any of the Video IP Listed below.
This issue has been resolved in the Video Timing Controller v6.0 (Rev1) in Vivado Design Suite 2013.2 or later.