My ISE System Generator project included a CE pin at the top level of the Sysgen block in the HDL file generated.
This was connected in my overall system. I have now migrated my design from ISE or Vivado 2012.4 to Vivado 2013.1 and there are errors due to this CE pin being expected in the design.
Where has this pin gone?
Was this a planned modification?
How do I work around the issue?
The top level CE port was introduced in ISE System Generator, however that port was always left unconnected.
This was misleading to many customers as they thought it was truly a clock enable pin.
As part of a System Generator re-write to support Vivado tools, this was removed and it will lead to possible issues with port matching in designs being migrated from ISE to Vivado design tools.
Customers will need to modify their original instantiations of the Sysgen project to remove the top level CE pin.