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AR# 56052

2013.2 Vivado - The net from OLOGIC to PAD connects the incorrect pin of OLOGIC in device view


In the Vivado 2013.2 and PlanAhead 14.2 tools, with a 7k325-fbg900-2 project, I open the implemented design and I find the Pin D1 of OLOGIC connects the OUTBUF of J18[Port dout[0]] in device view, but the TQ/OQ of the OLOGIC should be used to connect the OUTBUF of J18 (as shown in the image in the Solution section below). The connection in FPGA_Editor is correct, so it appears to be a display issue in the device view.



This is only a display issue. The issue is fixed in Vivado Design Suite 2013.3.

AR# 56052
Date 10/07/2013
Status Archive
Type Known Issues
  • PlanAhead - 14
  • Vivado Design Suite - 2013.2
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