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AR# 56066

7 Series FPGAs GTX/GTH/GTP Transceivers: Optimal RX Buffer Settings - CLK_COR_MIN_LAT and CLK_COR_MAX_LAT

Description

This answer record covers how to select the optimal settings for the RX buffer - CLK_COR_MIN_LAT and CLK_COR_MIN_LAT in the 7 Series FPGAs GTX/GTH/GTP Transceivers.

Solution

The CLK_COR_MIN_LAT and CLK_COR_MAX_LAT are attributes of the RX elastic buffer and impact clock correction, buffer latency and channel bonding. 

The 7 Series FPGAs Transceivers Wizard selects an optimal value for CLK_COR_MIN_LAT and CLK_COR_MAX_LAT based on the application requirements. These values selected by the wizard must be followed to maintain optimal performance and should not be overridden.

AR# 56066
Date Created 05/17/2013
Last Updated 05/22/2013
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT